TR-2013-04
Calibrating the Relationship between Hardware Customization and Energy Efficiency
Apala Guha; Yao Zhang; Raihan ur Rasool; Andrew A Chien. 11 July, 2013.
Communicated by Andrew Chien.
Abstract
With Dennard scaling at an end, chip-level performance scaling is heavily dependent on both parallelism (multicore and other dimensions) as well as customization. One major challenge to heterogeneous architecture is to effectively balance general-purpose coverage, customization for energy efficiency, and programmability. A central challenge for 10x10 or any broad-based heterogeneous architecture approach is determining the exact micro-engines that will compose a core given the large number of different choices for micro-engines and combinations. It is more generally useful to develop an abstract methodology for evaluating micro-engine candidates by modeling the relationship between the degree of hardware customization and benefit. We develop such a model based on extant accelerator designs which enables assessment of the benefits of architecture customization with full custom design and physical optimization.
Original Document
The original document is available in PDF (uploaded 11 July, 2013 by
Andrew Chien).
